As digital electronic processing systems trend toward higher operating frequencies and smaller device geometries, power management has become increasingly important to prevent thermal overload while maintaining system performance and prolonging battery life in portable systems.
The two principal sources of power dissipation in digital logic circuits are static power dissipation and dynamic power dissipation. Static power dissipation is dependent on temperature, device technology and processing variables and is composed primarily of leakage currents. Dynamic power dissipation is the predominant loss factor in digital circuitry and is proportional to the operating clock frequency, the square of the operating voltage and the capacitive load. Capacitive load is highly dependent on device technology and processing variables, so most approaches to dynamic power management focus on frequency and voltage control.
Digital design architectures are characterized as having a master or controller interoperating with a number of devices on a shared bus. One conventional approach is to have all peripheral devices connected on a communication bus to be powered from a common power distribution system. The power management algorithms will enable or disable devices along this power distribution system as needed, in order to conserve energy from devices when they are not required for system operation. The means to enable and disable devices is controlled by software, typically by the input/output (I/O) controller of the serial bus.